Application Portal Note: The deadline for the 2026 program cycle is June 1, 2025 23:59 (Pacific Time) Application Portal Applicant Information: arrowup6 Name * Position * Years in Position * Affiliation * Email * Please upload your CV. * Drop a file here or click to upload Choose File Maximum file size: 5MB Area of Teaching and Research * Optional: Supplemental information about department and university (e.g., degrees offered, undergraduate and graduate student enrollment, student demographics, etc..) CEMiD Program: Please read the following diagram carefully. Experience with IC Design and Tapeout: arrowup6 Have you taught a “tapeout” class before? If yes, please provide details about the course structure, CAD tools used, number of students and TAs, process node and foundry, and course outcomes. * Do you have experience with Cadence or Synopsys tools? * Plan for Tapeout Class: arrowup6 What is your envisioned course sequence and proposed semester/quarter for the tapeout class? Shown below are some examples: Quarter Systems Semester Systems * Provide a brief syllabus for your proposed tapeout course. * Drop a file here or click to upload Choose File Maximum file size: 10MB What are the pre-requisite courses for your proposed tapeout class? Will students be able to take these pre-requisites before the tapeout class? Are the pre-requisite courses analog-focused, digital-focused or both? * What is the availability of Cadence and/or Synopsys at your school? Is there a server infrastructure with tool licensing to support the tapeout class? Will students learn Cadence or Synopsys tools in pre-requisite courses or will they learn these tools in the tapeout class? * What design types (Analog, digital, analog mixed signal) will be supported in the tapeout class? * What would the cost be for one TA for one term? * What is your rough estimate of the enrollment in the first year of offering the class? If there is an existing class, what is the projected enrollment increase if you get additional support from CEMiD? * What would the project format be? For example, individual blocks designed by small (2-3 student) teams? A large SoC project designed by the entire class? Something in between? * How many chips do you estimate will be taped out? (CEMiD will allocate approximately 0.4mm² per student in TSMC180) * Do you currently have NDAs with MUSE/TSMC? If not, what is your plan/timeline for getting NDAs signed? * In which term(s) will the students design their PCBs and test their chips? * What are the existing lab and measurement facilities at your university that will be used for testing the chips? What kind of basic lab equipment, e.g., power supplies, oscilloscopes, function generators, is available? * Will you need to borrow or purchase any test equipment? What type of equipment? * Submit If you are human, leave this field blank. This form is protected by reCAPTCHA and the Google Privacy Policy and Terms of Service apply.
